This invention generally relates to an embedded dynamic random access memory (embedded DRAM), and more particularly, to a high-performance DRAM architecture utilizing gain cells.
Memory arrays constructed of six transistor static memory cells (6T SRAMs) are generally known to have faster access time and cycle time when compared to single-ended dynamic cells.
FIG. 1A shows a transistor level schematic of a conventional 6T SRAM cell 10 consisting of four NMOS transistors 1, 2, 5, and 6, and two PMOS transistors 3 and 4. PMOS 3 and 4 and NMOS 5 and 6 form a CMOS cross-coupled latch, which maintains a data bit as a storage element. NMOS transistors 1 and 2 couple nodes 7 and 8 to biltlines BL1 and BL2 when activated by wordline WL, allowing the data bit to read to or written from BL1 and BL2. On the other hand, single-ended dynamic cells are known to be smaller and benefit from significantly reduced soft-error-rate at small geometries.
FIG. 2A is a transistor level schematic of a conventional single-ended dynamic cell 20. It consists of one NMOS transistor 21 and capacitor 22 (1T DRAM cell). When the wordline WL is activated, NMOS 21 couples capacitor 22 to the bitline BL, allowing the data bit stored in capacitor 22 to be read to or written from BL.
Several reasons exist to explain the difference in performance. From a functional standpoint, the SRAM cell 10 shown in FIG. 1B can be described as one having three signal connections attached to each cell consisting of one storage element and two switches 11 and 12. These are: wordline (WL) and bitlines 1 (BL1) and 2 (BL2). Cells are arranged in a matrix formation with a wordline connecting a plurality of cells in one direction and bitlines in an orthogonal arrangement. Switches 11 and 12 are controlled by wordline WL such that storage element 15 can be accessed by bitlines BL1 and BL2. Data is preserved in the SRAM cell for many cycles as long as power is maintained, and as long as the wordline servicing the cells is not activated. In a non-activated condition, because switches 11 and 12 are opened, the SRAM cell presents a high impedance to the BL1 and BL2 connections. When the wordline is activated, switches 11 and 12 couple storage element 15 to bitlines BL1 and BL2. As a result, the SRAM cell displays a different impedance to bitlines BL1 and BL2 depending upon the state of the memory cell. For a cell storing a logic ‘1’, BL1 displays a lower impedance than BL2 at an impedance value that is slightly less than that in the non-activated case. A logic “1” represents the condition necessary for the CMOS cross-coupled latch in FIG. 1A to maintain a “0” and “1” at nodes 7 and 8, respectively.
Assuming that BL1 and BL2 are precharged to VDD, the impedance of NMOS switch 1 in FIG. 1A is lower than that of NMOS switch 2. For a cell storing a ‘0’, bitline_2 port will have a lower impedance than the bitline_1 port which, in turn, will display an impedance that is slightly less than the non-activated case. Thus, a “0” is the state wherein the CMOS cross-coupled latch maintains a 1 and 0 at nodes 7 and 8, respectively. Assuming having BL1 and BL2 precharged to VDD, then, NMOS switch 2 impedance is lower than the impedance of NMOS switch 1. This difference in impedances can be used to sense the state of the memory cell using one of several existing techniques. The state of the static memory cell is not disturbed by reading it; hence it is known to have a non-destructive read-out (NDRO). The cell is written by asserting the wordline while forcing a reference voltage on bitline_1 to write one state, or by forcing a reference voltage on bitline_2 to write the other state. If no bitline is forced (or if both are forced to the same direction), the cell will not be written, but instead will maintain its previous state. This is known as a non-destructive write (NDW).
The aforementioned characteristics are used to enhance performance using the following techniques since the read-out operation is nondestructive and the bitlines may be precharged back to their ‘ready’ state while the wordline is still activate. This characteristic makes it possible to reduce the time of a random access cycle. When a read-out is nondestructive, it is possible to multiplex several bitlines into a single sense amplifier, allowing the use of a larger area for each sense amplifier, and hence more complex, higher performance circuits. Moreover, since bitlines produce differential signals from each cell, the bitline signal is ‘self-referenced’, essentially reducing noise, improving the signal/noise ratio, and allowing a faster amplification of the signal. Furthermore, since the SRAM cell develops an impedance difference when read, it is possible to use current sensing techniques to sense the signal. These are known to be faster than voltage sensing techniques (traditionally used to sense dynamic cells) particularly for arrays having many bits per bitline. Since the SRAM cell can be read nondestructively (NDRO), the cell need not be written-back after it is read-out (as compared to traditional dynamic cells). Also, because the SRAM cell enables a nondestructive write (NDW), it is possible to perform a write operation only for selected cells even if more cells are activated by the corresponding wordline. Unselected data bits are typically maintained by floating bitlines (or by forcing both bitlines to high). Accordingly, the non-destructive read (NDRO) and non-destructive write (NDW) features have the most significant impact on the cycle time of a conventional DRAM cell array when compared to an SRAM cell.
From a functional standpoint, the single ended dynamic cell 20 can be described as one having two signal connections attached to each cell including one storage element 22 and one switch 21 (FIG. 2B). The connections are: wordline (WL) and bitline (BL). Because of the nature of the dynamic cell, when WL is activated, data in the storage element is destroyed (destructive read). The destroyed data needs then to be written back into the storage element increasing the read cycle time. Because of the write back requirement, DRAMs typically use a CMOS cross-coupled sense amplifier SA. Additionally, the write cycle time is equal or slower than the read cycle time, unless all the bits coupled to the wordline are simultaneously written. This may be explained by the fact that unselected cells for the write operation are destroyed in a manner similar to the destructive read operation, requiring a sensing and write back operation (read modified write), necessitating a longer write cycle time.
Accordingly, it is important to solve these two problems to enable the SRAM like cycle time. Techniques are known to utilize a destructive read/destructive write 1T1C DRAM cell in combination with a write-back buffer array to realize a dynamic memory with cycle time that approaches that of an SRAM. One known technique is a memory architecture in which the read-out of one DRAM array occurs simultaneously with the write-back operation in a separate DRAM array of the same memory. A buffer array is used to resolve data conflicts. Data management techniques inherent to this solution, however, tend to increase the access time. Hence it is difficult to use such a technique to achieve an SRAM-like access time.
FIG. 3A shows a prior art single-ended multi-port destructive write memory cell 30 consisting of a storage element 33 and two switches (31 and 32). The single ended multi port destructive write memory cell is characterized by having four wires connected to each cell:
a read bitline (RBL) traversing the array in one direction,
a write bitline (WBL) traversing the array in a direction parallel to the read bitline;
a read wordline (RWL) traversing the array of cells in a direction orthogonal to the bitlines;
and a write wordline (WWL) traversing the array of cells in a direction parallel to the read wordline.
Data is stored in the cell for as many cycles as necessary as long as the read wordline and write wordline are not activated. The cell displays high impedance at its read bitline port as long as the read wordline is not activated. When the read wordline RWL is activated, the switch 30 couples storage element 33 to read bitline RBL. This enables the nondestructive read cell to provide an impedance to the read bitline (RBL) which depends on the logic value stored in a cell similar to the 6T SRAM cell. This occurs in the class of single-ended multi-port cells which have nondestructive read-out.
FIGS. 3B-3C show conventional nondestructive read and destructive write memory cells comprising three transistors (3T cell) and two transistors (2T cell), respectively, or a destructive read cell such as one having a single capacitor, wherein the storage element shares the charge that it is stored in the capacitor in the read bitline (RBL). This occurs in the class of single-ended multi-port cells which have destructive read-out.
FIG. 3D shows a prior art destructive read and destructive write memory cell consisting of two transistors and one capacitor (2T 1C cell).
Regardless whether a 3T, 2T, or 2T 1C cells are used, when a write wordline is activated, the cell takes on the logic state that is forced onto the write bitline by opening switch 32 (FIG. 3A), coupling it to the write BL (WBL). Every cell which is connected by a write wordline being activated is written into. There is no option for activating a wordline and having the cell maintain its previous state because of a destructive write. Therefore, it is required to write all the bits coupling to the activated WWL simultaneously. Otherwise, the write cycle time is limited by the read modify write back operation similar to the DRAM. However, writing all the bits along the wordline concurrently requires rearranging the data lines and associated drivers with the same periodicity as the memory cells. Such a solution requires significant area and hence is expensive. Also, the number of cells coupled to a wordline must be equal or less than the number of the write data bits. This requirement is not practical for a “narrow” I/O organization, such as x 16, or even for x 32 or x 64. Using a single-ended multi-port non-destructive write memory cell may overcome the problem. However, it requires at least an equal number, or preferably, more transistors than the conventional 6T SRAM cell and is, therefore, undesirable for being expensive.
In a typical destructive read array, the read cycle consists of a read-out, a write-back and a precharged phase. In the conventional destructive write array, all the data bits coupled to a wordline are simultaneously written. Otherwise, the write cycle consists of a read-out, a modify-write-back and a precharged phase (read modified write). Hence the typical operation of a single-ended destructive write multi-port memory cell ends up having a longer cycle than that of a nondestructive read /write 6T SRAM.